1. Field of the Invention
The present invention relates to a latch circuit used to latch address signals or control signals of a semiconductor memory device. In particular, the present invention relates to a clock sync latch circuit by which input signals opposite in polarity to each other are outputted from each of the rising and falling edges of one clock.
2. Description of the Prior Art
Below, a conventional latch circuit will be explained in detail with reference to the attached drawings.
FIG. 1 shows a conventional latch circuit, which includes a first differential amplify circuit section 10 to the gate of which a clock signal is applied; a second differential amplify circuit section 20 to the gate of which an inverted clock signal is applied; and a data select circuit section 30 for selecting any one output of the two outputs of the first and second differential amplify circuit sections 10 and 20 to output it.
In FIG. 1, the first differential amplify circuit section 10 consists of first and second P channel MOS transistors MP1 and MP2, which are connected with a cross couple structure between the power supply Vcc; a first node N1 and a second node N2; a first N channel MOS transistor MN1 to the gate of which is applied an input voltage Vin and connected between the first node N1 and a third node N3; a second N channel MOS transistor MN2 to the gate of which a reference voltage Vref is applied and connected between the second node N2 and the third node N3; and a third N channel MOS transistor MN3 to the gate of which a clock signal CLOCK is applied and connected between the third node N3 and the ground voltage Vss. The second differential amplify circuit section 20 is consisted of third and fourth P channel MOS transistors MP3 and MP4, which are connected with a cross couple structure between the power supply Vcc, a fourth node N4 and a fifth node N5; a fourth N channel MOS transistor MN4 to the gate of which the input voltage Vin is applied and connected between the fourth node N4 and a sixth node N6; a fifth N channel MOS transistor MN5 to the gate of which the reference voltage Vref is applied and connected between the fifth node N5 and the sixth node N6; and a sixth N channel MOS transistor MN6 to the gate of which an inverted clock signal /CLOCK is applied the wherein the clock signal CLOCK is inverted by an inverter I1 and connected between the sixth node N6 and the ground voltage Vss. Also, the data select circuit section 30 selects any one of the output N2 of the first differential amplify circuit section 10 or the output N5 of the second differential amplify circuit section 20 to output it.
The operation of the conventional latch circuit as constructed above is as follows.
When the clock signal CLOCK is HIGH, the second differential amplify circuit section 20 does not operate. Instead, only the first differential amplify circuit section 10 operates. If the input voltage Vin of the first differential amplify circuit section 10 is higher than the reference voltage Vref, the first, third N channel MOS transistors MN1, MN3 are turned-on and the voltage level of the first node N1 becomes LOW to turn on the second P channel MOS transistor MN2 having a cross couple structure. Therefore, the voltage level of the second node N2 becomes HIGH and inputted to the data select circuit section 30. However, if the input voltage Vin is lower than the reference voltage Vref, the voltage level of the second node N2 becomes LOW and inputted to the data select circuit section 30.
On the other hand, when the clock signal CLOCK is LOW, the first differential amplify circuit section 10 does not operate. Only the second differential amplify circuit section 20 operates. If the input voltage Vin of the second differential amplify circuit section 20 is higher than the reference voltage Vref, the fourth, sixth N channel MOS transistors MN4 and MN6 are turned-on and the voltage level of the fourth node N4 becomes LOW to turn on the fourth P channel MOS transistor MN4 having a cross couple structure. Therefore, the voltage level of the fifth node N5 becomes HIGH and inputted to the data select circuit section 30. However, if the input voltage Vin is lower than the reference voltage Vref, the voltage level of the fifth node N5 becomes LOW and inputted to the data select circuit section 30.
However, as described above, the conventional latch circuit needs two latch circuits which are synchronized by means of the two clock signal CLOCK, /CLOCK which have opposite polarities each other so that one input signal is inputted to output data from the rising and falling edges of the clock.
Moreover, when the circuit operates at high frequency, and a skew occurs between the clock signal CLOCK and the data, there exists a delay because the inverted clock signal /CLOCK of the clock signal is one passed through the inverter I1. At this time, if a skew occurs between the inverted clock signal /CLOCK of the clock signal and the data, there exists a problem in that the data outputted from the rising and falling edges of the clock collide each other, thereby causing a malfunction in the circuit.